MLCCs - The Next HBM? | Long-term Investing : Thematic

Rubin & Rubin Ultra to drive a step-function in per-rack MLCC content — ranking the global producers

A quiet 5¢ ceramic component is becoming one of the most supply-constrained, ASP-positive parts of the AI build-out — and tier-1 producers are pricing it accordingly.

What is an MLCC? — The 30-Second Primer

A Multi-Layer Ceramic Capacitor (MLCC) is a tiny passive electronic component — typically smaller than a grain of rice — that stores and releases electrical charge. Mechanically, it is a stack of alternating layers of ceramic dielectric material (usually barium titanate) and metal electrodes, fused together at high temperature. The more layers (up to 1,000+) and the thinner each layer (sub-1 micron in advanced parts), the higher the capacitance you can pack into a given footprint.

MLCCs do two things on a circuit board: (i) smooth out voltage by absorbing and releasing charge faster than the power supply can respond, and (ii) filter noise by shunting unwanted high-frequency signals to ground. On any given motherboard, GPU package, or server power module, you will find hundreds to thousands of them clustered around the chips they support — the more current the chip draws and the faster it switches, the more MLCCs you need around it. They are individually cheap (fractions of a cent each), collectively ubiquitous (one trillion-plus produced globally per year), and increasingly the chokepoint in AI server builds.

The Top-Down Thesis

A traditionally commoditised passive component is being repriced as a strategic AI input — driven by content explosion, capacity allocation discipline, and structural ASP support from the tier-1 oligopoly.

• 01 Content per rack is exploding, not just per server.

  An AI server uses 10–15× the MLCCs of a general-purpose server, and a single Nvidia GB300 NVL72 rack now requires ~440,000 MLCCs (Morgan Stanley channel checks). Vera Rubin VR200 NVL72 is estimated at ~600,000 (+36%), with Rubin Ultra (Kyber, NVL576) expected to push this materially higher as GPU TDP rises to ~1,800W per unit and switching frequencies climb.

• 02 Architectural substitution is amplifying the volume signal.

  Higher power demands are forcing a wholesale shift from aluminium polymer capacitors to MLCCs at the VRM/decoupling stages — SEMCO has explicitly flagged this as the dominant architectural trend in AI server power. This is a one-way trade-up: lower ESR, smaller footprint, and most importantly a multi-vendor supply chain (versus single-vendor polymer caps).

• 03 The spec is migrating up the value curve.

  Rubin-class power delivery requires high-capacitance, low-ESL, ultra-small form factor parts — Murata’s 47µF 0402 MLCC (world-first, July 2025) is the canonical example. These are 5–10× ASP of commodity 0402 parts and the manufacturing yield is materially lower, both of which compound the value capture for tier-1 producers.

• 04 Supply is structurally tight and the tier-1s are pricing it

  Lead times on high-cap / low-ESL grades have stretched from 8–12 weeks (late 2024) to 26–40 weeks (2026). Murata implemented its first price hike in three years (+15–35% on AI-server and auto grades, eff. April 2026); Taiyo Yuden raised +6–13% (eff. May); Samsung Electro-Mechanics is targeting double-digit hikes; Yageo and Walsin have followed in Taiwan. SEMCO’s 2026 capex is set to more than double YoY explicitly for AI MLCC and FCBGA.

• 05 Oligopoly economics protect the trade.

  The top 5 (Murata, SEMCO, Taiyo Yuden, TDK, Yageo) control ~68% of the high-end MLCC market; Murata alone holds an estimated ~70% of AI server-grade MLCC supply per industry channel checks. Customer qualification cycles run 12–18 months, erecting hard barriers to share migration even as Chinese capacity scales in commodity grades.

• 06 This is the HBM analogue in passives.

  The setup mirrors HBM in 2023 — a quietly bottlenecked, design-in-protected component sitting one layer below the headline AI chip, where content growth and ASP compound through the cycle. The window to position ahead of consensus is finite; Rubin VR200 ships H2 2026.

A note on valuation: Several names in this report have begun re-rating, and we acknowledge the initial move. Our conviction, however, is forward-looking: it is the combination of share price momentum validating the thesis and earnings compounding as ASP hikes and volume mix flow through to margins that we expect to propel further gains. The re-rating is a confirmation that the market is beginning to see what we see and that the earnings inflection is still ahead.

Why the Market Is Still Mispricing This

Buried in Industrials CoverageMLCC names are covered by industrials/electronics analysts, not semis or AI infrastructure desks. The AI content-growth narrative has not transmitted into consensus estimates, particularly on FY27 ASP assumptions.

Cycle Pattern RecognitionInvestors anchored to the 2018–2019 and 2022–2023 MLCC down-cycles (consumer / smartphone-driven) are underweighting the secular shift toward AI / auto, which now represents the highest-margin slice of the mix.

Index / FX Optical DragJapanese names (Murata, Taiyo Yuden, TDK) carry JPY translation noise and modest index sponsorship; Korean and Taiwanese names sit outside many global tech benchmarks — creating a true alpha pocket vs. consensus AI exposure.

The Content Math — MLCCs Per Rack Across the Nvidia Roadmap

The Content Math — MLCCs Per Rack Across the Nvidia Roadmap

Sources: Morgan Stanley channel notes, TrendForce, Findchips supply tracker, SEMCO IR, Nvidia GTC 2025 disclosures, LC IC estimates. GPU counts per Nvidia OCP specifications. Rubin Ultra MLCC estimate is LC base case extrapolation from per-GPU MLCC density implied by GB300/Rubin disclosures applied to 8× GPU count — to be validated against supply chain disclosures closer to launch.

Why the Content Is Going Up — Five Independent Drivers

• 01 GPU TDP rising faster than voltage can drop.

  Rubin GPUs run at ~1,800W on sub-1V rails, meaning >1,800A of current at the package — every 100A of incremental current draw requires meaningfully more decoupling capacitance close to the chip, scaling roughly linearly with TDP.

• 02 Aluminium polymer cap → MLCC substitution.

  SEMCO and Murata have publicly flagged that high-CV mid-to-large MLCCs are replacing polymer caps at the VRM input stage. This is a 1.5–2× volume uplift on a per-board basis, independent of GPU performance scaling.

• 03 NVLink switch trays and CX-9 NICs.

  Each 9-switch NVLink tray plus ConnectX-9 800G/1.6T networking introduces its own dense MLCC clusters for SerDes power filtering — a meaningful incremental driver beyond the GPU compute trays themselves.

• 04 Embedded / landside MLCCs inside the package.

  Next-gen Rubin packaging integrates MLCCs inside the substrate (landside / embedded) to reduce loop inductance — an entirely new SKU category at premium ASPs which doesn’t displace board-level MLCC count.

• 05 Higher rack density / NVL144 / NVL576.

  Nvidia’s roadmap (NVL72 → NVL144 → NVL576 Kyber) multiplies GPU count per rack — Rubin Ultra Kyber alone is 8× the GPU density of NVL72, with corresponding multiplication of decoupling requirements.

Supply-Side: The Squeeze Is Already Showing

Scoring Framework — Three Pillars, Each Scored 1–5

The thematic case is broad, but capturing it through the right names requires discrimination. A pure-play, technologically advantaged, well-qualified producer will see a multi-x earnings impact from the content explosion; a diversified conglomerate with a small MLCC business will see only a marginal lift even if its absolute MLCC dollars rise meaningfully. We score each player across three orthogonal pillars and take a simple average for the composite ranking. Pillar selection and rationale below.

Why These Three And Not Others — Pillars Considered & Excluded

Capacity / scale. Considered but excluded — capacity is a function of the three pillars above (technology gates which capacity is relevant; qualification gates which capacity is monetisable; purity captures the share of capacity going to the thematic). Adding it would double-count.

Geographic risk / sovereign exposure. Considered but excluded from the composite — handled as a separate portfolio-construction overlay rather than a scoring axis. Taiwan-domicile concentration and China-customer exposure are real risks but should be sized at the portfolio level, not used to handicap individual security selection.

Valuation. Deliberately excluded from the ranking. The ranking is a quality / exposure screen; valuation is the second step in position-sizing and is handled in the deep-dive notes to follow. Building valuation into the screen would conflate “what to own” with “what to pay” — they answer different questions.

ESG / governance. Acknowledged as a relevant overlay (particularly for Chinese names) but does not drive thematic selection at this layer.

Composite & Decision Rules

Composite score = simple average of the three pillars, rounded to one decimal. We deliberately use an equal weight rather than a weighted average: each pillar is a distinct gating condition, not a proportional contributor. A score of 5 in technology with a 2 in qualification is essentially un-investable for this thesis regardless of average; the simple-average frame surfaces these imbalances clearly in the underlying scores.

AI-server torque is reported as a qualitative tag alongside the composite — it indicates the directional sensitivity of group earnings to incremental AI-server MLCC demand, accounting for both the purity and the qualification scores. This is the tag we use to size positions, not the composite alone.

Ranking tie-breaks are resolved in favour of higher purity, on the rationale that pure-play exposure is the dominant leverage variable in any thematic basket. Where purity is tied, qualification breaks the tie.

The Top 10 — Global MLCC Producers Ranked for the Rubin Content Thesis

* PDC: capacitors + dielectric powder combined; powder is sold to other MLCC producers as well. MLCC revenue shares are LC estimates from latest available company filings and industry reports (TrendForce, Mordor Intelligence, BigGo, Digitimes channel checks). Highlighted rows = top-3 conviction names. Composite = simple average of three pillars rounded to one decimal. Maruwa (5344 JP) intentionally excluded — primarily a ceramic substrate (AlN/Si3N4) play; MLCC is a small ancillary line and should be evaluated under the power-semis ceramic substrates theme separately.

Top-3 Per-Name Conviction Snapshot

Suggested Portfolio Construction

Core (~60% of basket): Murata (#3) and SEMCO (#2) as the quality anchors — large-cap, liquid, dominant share, and price-setting power. Beta sleeve (~25%): Taiyo Yuden (#1) for the pure-play ASP leverage. Taiwan diversification (~10%): Yageo (#4) or Walsin (#5) for order-transfer benefits as Japanese/Korean tier-1s ration capacity to marquee customers. Small-cap optionality (~5%): PDC (#6) on the dielectric-powder chokepoint angle — illiquid, watchlist-sized only. The TDK and Kyocera dilution penalty makes them inferior expressions of this specific thesis despite their technical capability; better held for other reasons.

The above sizing is illustrative for a single-theme basket and assumes an active equities sleeve. Sizing within an existing portfolio mandate must be calibrated against the client’s existing AI infrastructure exposure (Nvidia, hyperscalers, semiconductor equipment, power & cooling names) to avoid stacking correlated factor risk. This is not investment advice or a client suitability assessment; figures are based on publicly available industry data and channel checks, some of which are estimates and have not been independently verified against Bloomberg fundamentals. Any client distribution requires Investments & Compliance review.

Author

Drishtant Chakraberty, CFA

Vice President — Equity Research

Lighthouse Canton